1. Technical Field
The present invention relates to clock edge detection circuits that detect whether or not the edges of two clock signals coincide with each other.
2. Related Art
In general, a clock edge detection circuit is a circuit that is built in a semiconductor integrated circuit for conducting an operation test of a circuit such as a PLL (phase locked loop) circuit that generates an output signal with a phase synchronized with an input signal.
FIG. 5 shows an example of a structure of a conventional clock edge detection circuit. The clock edge detection circuit detects whether or not an edge of a reference clock signal R that becomes an input signal of a PLL circuit coincides with an edge of a comparison clock signal F that is an output signal of the PLL circuit. The reference clock signal R is inputted in one of input terminals of an EOR (Exclusive OR) circuit 1, and the comparison clock signal F is inputted in the other of the input terminals.
When a time difference is present between the edge of the reference clock signal R and the edge of the comparison clock signal F, the EOR circuit 1 outputs a pulse having a width corresponding to the time difference. The output signal of the EOR circuit 1 is supplied to a clock input C of a flip-flop 2. In the flip-flop 2, a data input D is at a high level, and therefore a level of an output Q thereof becomes high, when the EOR circuit 1 outputs the pulse. The flip-flop 2 is reset and the operation described above is repeated; and when the output Q of the flip-flop 2 does not become a high level, it can be said that the edge of the reference clock signal R and the edge of the comparison clock signal coincide with each other.
However, the conventional clock edge detection circuit has to process a pulse with a very narrow width when an edge of the reference clock signal R and an edge of the comparison clock signal F are close to one another. As a result, the operation is apt to become unstable due to noises, deviations in circuit elements, temperature changes and so forth.
In view of the above, it is an object of the present invention to provide a clock edge detection circuit that can stably detect whether or not the edges of two clock signals coincide with each other within a predetermined time range.
To solve the problem described above, a clock edge detection circuit in accordance with the present invention comprises: a first delay circuit that delays a first clock signal and outputs a first delay clock signal; a second delay circuit that delays a second clock signal and outputs a second delay clock signal; a first retaining circuit that retains a level of the first delay clock signal at an edge of the second clock signal; a second retaining circuit that retains a level of the first clock signal at an edge of the second delay clock signal; and a logical circuit that outputs, based on the output signals of the first and second retaining circuits, a detection signal representing whether or not an edge of the first clock signal and an edge of the second clock signal are within a predetermined time range.
Here, each of the first and second delay circuits may include a buffer circuit. Alternatively, each of the first and second delay circuits may include a variable delay circuit. Also, each of the first and second retaining circuits may include a flip-flop. Furthermore, the logical circuit may provide a logical product of a reversed logical value of an output signal of the first retaining circuit and an output signal of the second retaining circuit.
By the clock edge detection circuit of the present embodiment thus composed, positions of the edges are detected by using the first and second clock signals and the clock signals having specified delays added to these clock signals. As a result, it is possible to stably detect whether or not the edge of the first clock signal and the edge of the second clock signal are within a predetermined time range.